IBM's 1nm Node

IBM recently released a new one nanometer node, with transistors that are .7nm, or 7 angstroms wide. We won’t see chips with transistors this small until maybe 2030, but it is an innovation that seems unique to IBM. With how much compute is necessary to train these LLMs, packing more compute in an equally sized chip is going to be great.

The bottleneck in production of chips this small is from ASML, who makes the technology to produce the chips. The current frontier ASML machine, the high NA EUV TWINSCAN EXE:5000, will only be able to print down to 8nm in resolution. For reference Intel’s 14A process has an back end of line pitch of 20-22 nm, while this new IBM stack drops it to below 18nm.

IBM made this implementation by making a new nanostack architecture, where transistors scale vertically as well as horizontally. This builds on the ideas from gate all-around transistors, and should scale like how we saw FinFET and Gate All Around transistors scale.

I am excited to see where this leads, but I have my doubts in the yield rates for these future processes. Intel’s 14A nodes reportedly suffer from low yields of less than 60%, while mature processes often exceed 90%. If ASML can scale down and TSMC can scale up, we are in for a good extension of Moore’s law.